FIG. 1 is a functional block diagram of a conventional first order or single bit sigma delta analog-to-digital (A/D) converter (ADC) 100 that converts an analog input voltage Vin into a corresponding digital output signal DO. The analog input voltage Vin is applied to a non-inverting input of a summation circuit 102 which also receives an analog feedback voltage AF from a single-bit digital-to-analog converter (DAC) 104. The DAC 104 develops the analog feedback voltage AF response to the digital output signal DO. The summation circuit 102 subtracts the analog feedback voltage AF from the input voltage Vin to develop an analog output AO and outputs the analog output to a low pass filter 106. The low pass filter 106, which may be an integrator, filters the analog output AO to generate a filtered analog output FAO and applies this filtered analog output to a quantizer 108. Where the converter 100 is a single-bit circuit, the quantizer 108 is a comparator which compares the FAO output from the filter 106 to a reference voltage and generates the digital output signal DO responsive to this comparison.
In operation, where the converter 100 is a single bit circuit the converter generates a bitstream or series of binary values (0 and 1) for the digital output DO which corresponds to the analog input voltage Vin. The detailed operation of the conventional sigma delta converter 100 is well understood by those skilled in the art and thus, for the sake of brevity, will not be described in more detail herein. A decimation filter (not shown) typically receives the digital output DO and converts the bitstream into a slower stream of multi bit samples, each sample being a digital value representing the value of the analog input voltage Vin. The rate at which the converter 100 operates is typically indicated through a sampling frequency Fs that indicates the rate at which the analog input voltage Vin is sampled and the rate at which the components 102-108 operate on samples of the analog input voltage to generate a corresponding digital output DO for each sample of the analog input voltage. When the converter 100 is a multi-bit converter the quantizer 108 is no longer a single comparator but instead is itself an analog-to-digital converter such as a flash ADC including a bank of comparators.
The converter 100 achieves high-resolution analog-to-digital conversion through the concepts of over-sampling and noise shaping. A system is deemed an over-sampled system when the sampling frequency Fs is many times greater than the minimum required sampling rate given by the Nyquist sampling criteria (i.e., minimum sampling frequency must be twice the maximum frequency Fin of the input signal Vin). For example, in an audio system the highest audible frequency Fin is 20 KHz so that the minimum sampling frequency or Nyquist frequency is 40 KHz (minimum Fs equals 2×Fin=2×20 KHz=40 KHz). The ratio of the sampling frequency Fs to the Nyquist frequency (Fs/2Fin) is defined as the over-sampling ratio (OSR).
Quantization is the process by which a signal is assigned or “quantized” to one among a finite set of levels and this process inherently introduces error. For example, let an input signal be quantized into one of N values in a quantization set and let the distance between each level be Δ. If the input signal has a value exactly in between two levels, then the signal will have to be arbitrarily assigned to one of the two levels. By assigning the input signal to one of the two levels, an error of λ/2 has been introduced. This error is referred to as quantization error or quantization noise and is statistically independent of the input signal.
If the input signal is sampled at some frequency Fs such that Nyquist's sampling theorem is satisfied, then when the signal is quantized the power of the resulting quantization noise is spread between frequencies 0 to Fs/2. If the frequency band of interest is 0 to Fin, then it follows that increasing Fs will decrease the power of the noise within the band of interest. Mathematically it can be shown that doubling of the sample frequency results in a decrease of the in-band noise power by 3 dB, as will be appreciated by those skilled in the art. The greater the sampling frequency Fs the larger the bandwidth over which this noise power is distributed. If the sampling frequency is much greater than the frequency band of interest (0 to Fin), then the noise within the band of interest is reduced since the total noise power is distributed over a wider range of frequencies.
Using linear signal analysis it can be shown that the filter 106 will have a low pass characteristic to the input signal Vin and a high pass characteristic to the quantization noise, as will be appreciated by those skilled in the art. As a result, the quantization noise can be shifted or “shaped” to reside in a frequency band outside of the frequency band of interest such that this noise can later be filtered out without affecting the input signal. This is known as noise shaping. As previously mentioned, a decimation filter (not shown) receives the DO output. In addition, another low pass filter (also not shown) functions to filter out quantization noise that has been shifted to a higher range of frequencies through noise shaping. The converter 100 is able to achieve high conversion resolutions in the frequency band of interest (i.e., 0 to Fin) by the use of over-sampling and noise shaping. The amount of noise power in the frequency band of interest is a function of the OSR (Fs/2Fin), the order of the filter 106, and the number of bits of the quantizer 108.
Because the noise power in the frequency band of interest is function of the number bits of the quantizer 108, the signal-to-noise ratio (SNR) of the converter 100 is a function of the number of bits of the quantizer 108. The more bits of the quantizer 108 the lower the quantization noise. Accordingly, the use of a multi bit quantizer 108 is generally desirable. When the quantizer 108 is multi bit, however, the DAC 104 in the feedback path from the DO output to the summation circuit 102 must also be a multi bit DAC that develops a multi level analog feedback voltage AF.
One problem arising out of the use of a multi-bit DAC is that due to process variations, the analog elements used in the DAC, such as capacitive and current elements, can be mismatched relative to one another. These mismatches can cause errors among the different levels output from the DAC 104 and thereby result in errors in desired values for the analog feedback voltage AF. Such errors in the feedback voltage AF can result in increased SNR as well as increased total harmonic distortion (THD) of the converter 100. Increased THD can occur because the same errors will always occur between the same levels for the AF output from the DAC 104 (i.e., for the same values of the DO signal). This can add harmonic distortion to the DO signal. Since the feedback voltage AF from the DAC 104 is applied to the summation circuit 102, any errors in this voltage are effectively input to the converter 100m meaning that any errors in the AF voltage from the DAC will appear at the digital output DO of the converter.
To prevent such mismatch errors in the DAC 104 from affecting the AF output and thereby the DO output, the AF output must be corrected before it gets fed back in order to mitigate the resulting mismatch errors. Several conventional techniques have been utilized to compensate for such mismatch errors, with these techniques being collectively known as dynamic element matching (DEM) techniques. The fundamental principle of DEM techniques is to randomize the mismatch effects of the DAC 104 such that the errors are spread out across the frequency spectrum and thereby appear as random noise instead of appearing as noise at discrete tones or harmonics of the input signal Vin. Those skilled in the art will appreciate various DEM techniques commonly utilized, such as Data Weighted Averaging (DWA) and Individual Level Averaging (ILA). Each of these techniques tracks the past utilization of components in the DAC 104 to control the components selected for a current value of the AF voltage to be generated.
These DEM techniques work very well and have been well researched and implemented. The utilization of these techniques does, however, result in increased design cost, as well as increased area occupied by and power consumption of the converter 100. Another approach utilized in the art is a feed forward approach as shown in FIG. 2, which is a functional block diagram of a feed forward sigma delta converter 200 that receives an analog input voltage Vin and generates a corresponding digital output voltage DO. The feed forward sigma delta converter 200 includes a first summation circuit 202 coupled in series with a filter 204, a second summation circuit 206, and a multi bit quantizer 208 that provides the digital output DO of the converter. A multi bit DAC 210 receives the DO output and generates a corresponding feedback voltage AF that is applied to one input of the first summation circuit 202. The input voltage Vin is multiplied by a coefficient a6 in a feed forward path 212 and this value supplied as one input to the second summation circuit 206. The filter 204 includes five integrator stages 205a-3 and is a 5th order filter in the example of FIG. 2, with an output from each stage being multiplied by a corresponding coefficients a1-a5 and applied as an input to the second summation circuit 206.
In operation, the feed forward path 212 functions to add a Vin component to the input supplied to the multi bit quantizer 208 such that this component is supplied through the multi bit DAC 210 and subtracted out by the first summation circuit 202 (true since the output of DAC 210 is applied to an inverting input of the first summation circuit 202). In this way, the magnitude of the input signal Vin may be effectively cancelled out before this magnitude is supplied to the filter 204. Cancellation of the input signal Vin in this way enables the filter 204 to be designed to filter unwanted quantization noise, both real quantization noise and harmonics introduced by the multi bit DAC 210. This also reduces the dynamic range of the filter 204 and simplifies its design and implementation.
The cancellation of the input signal Vin is accomplished in the converter 200 as follows. Assume the multi bit quantizer 208, which would be an ADC, has a gain K and that the DAC 210 has a gain L. Accordingly, the input voltage Vin times the coefficient a6 should have a value such that (a6×Vin) cancels out all signals from the filter 204 that are applied to the remaining inputs of the second summation circuit 208. This is true since the input voltage Vin applied through summation circuit 202, filter 204, second summation circuit 206, quantizer 208 and DAC 210 experiences a gain of KL. The value of coefficient a6 is accordingly equal to 1/KL, meaning that a6 times the combined gain of the quantizer 208 and the DAC 210 (i.e., KL) is equal to 1. In this way, ((Vin×a6)=Vin/KL is input to the summation circuit 206, and this component of the out from this summation circuit then experiences the gain KL as it is fed back to the summation circuit 202, so that (Vin/KL)×K×L equals Vin. If the gain of the combination of the quantizer 208 and DAC 210 (KL) is assumed to be relatively constant over the range of operation of these components, then the coefficient a6 has a constant value over this range as well.
Note that the converter 200 includes the multi bit DAC 210 which, as previously discussed, requires the use of DEM techniques and the associated increased design cost and increased area occupied by and power consumption of the converter 200.